Study on the Developmental Written Performance by Enhancing Internal Parallelism of Solid State Drives

Most research of Solid State Drives architectures rely on Flash Translation Layer (FTL) algorithms and wear leveling; however, internal parallelism in Solid State Drives has not been well explored. In this research, I proposed a new strategy to improve SSD write performance by enhancing internal parallelism inside SSDs. The architecture includes an SDRAM buffer for buffering and scheduling write requests. The on-board DRAM buffer is used to buffer requests at the lower level of FTL because the identical logical block numbers may be translated to different physical numbers at various moments in FTL. To improve internal parallelism, when the buffer is full, the same amount of data will be assigned to each storage package in the SSDs. In this paper, all SSD configurations are exactly the same to avoid the performance difference from faster buffers or caches. To accurately evaluate performance, Study use both synthetic workloads and real-world applications in experiments. I compare the enhanced internal parallelism scheme with the traditional LRU strategy, because it is unfair to compare an SSD having buffer with an SSD without a buffer. The simulation results demonstrate that the writing performance of our design is significantly improved compared with the LRU-cache strategy with the same amount of buffer sizes.